# overview
My research areas include Computer-aided design of Very Large Scale Integration (VLSI) ICs, including logic and physical design automation.

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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4607 Graphics, Augmented Reality And Games

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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Intercellular Signaling Peptides And Proteins

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4009 Electronics, Sensors And Digital Hardware

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Intra- And Inter-chip Clock Synchronization

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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Differential Cascode Voltage Switch Logic (dcvsl)

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4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

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4606 Distributed Computing And Systems Software

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# educationAndTraining[].organization.label
The University of Texas at Austin - (Austin, Texas, United States)

# educationAndTraining[].organization.label
Indian Institute of Technology Kanpur - (Kanpur, Uttar Pradesh, India)

# educationAndTraining[].organization.label
University of California, Berkeley - (Berkeley, California, United States)

# awardsAndHonors[].label
Association of Former Students College-Level Teaching Distinguished Achievement Award, The

# publications[].label
Accelerating Circuit Simulation Using Graphics Processors

# publications[].label
A Robust C-element Design with Enhanced Metastability Performance

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A PTL based highly testable structured ASIC design approach

# publications[].label
A Single-supply True Voltage Level Shifter

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Novel Hardware Hash Unit Design for Modern Microprocessors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Flash-based Current-mode IC to Realize Quantized Neural Networks

# publications[].label
A Radiation Tolerant Phase Locked Loop Design for Digital Electronics

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Minimum Leakage Vector Computation using Weighted Partial MaxSAT

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A SAT-Based Scheme to Determine Optimal Fix-free Codes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Minimum Energy Near-Threshold Network of PLA Based Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Noise-based Information Processing Noise-based logic and computing: what do we have so far?

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Resource and delay efficient matrix multiplication using newer FPGA devices

# publications[].label
Accelerating Statistical Static Timing Analysis Using Graphics Processors

# publications[].label
Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
High-throughput VLSI implementations of iterative decoders and related code construction problems

# publications[].label
Introduction of On-Chip Crosstalk Avoidance

# publications[].label
Exploiting Leakage: Sub-threshold Circuit Design

# publications[].label
A design approach for radiation-hard digital electronics

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
SEU Hardened Clock Regeneration Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An Asynchronous Network-on-Chip Router with Low Standby Power

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast Circuit Simulation on Graphics Processing Units

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design Conclusions and Future Directions

# publications[].label
An FPGA-based Coprocessor for Hash Unit Acceleration

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A PTL based Highly Testable Structured ASIC Design Approach

# publications[].label
Decomposition techniques for efficient ROBDD construction

# publications[].label
Scaled Population Subtraction for Approximate Computing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Generalized buffering of PTL logic stages using Boolean division

# publications[].label
A Novel, Highly SEU Tolerant Digital Circuit Design Approach

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Timing Aware Partitioning for Multi-FPGA Based Logic Simulation Using Top-down Selective Hierarchy Flattening

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An ASIC Design Methodology with Predictably Low Leakage, using Leakage-immune Standard Cells

# publications[].label
On the improvement of statistical timing analysis

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations

# publications[].label
A novel clock distribution and dynamic de-skewing methodology

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Advanced Techniques in Logic Synthesis, Optimizations and Applications

# publications[].label
Application of Max-SAT-based ATPG to optimal cancer therapy design.

# publications[].label
Hardware Acceleration of EDA Algorithms Custom ICs, FPGAs and GPUs Introduction

# publications[].label
A single-supply true voltage level shifter

# publications[].label
Energy efficient and high speed on-chip ternary bus

# publications[].label
Memory-based cross-talk canceling CODECs for on-chip buses

# publications[].label
VIS: A system for verification and synthesis

# publications[].label
Sequential multi-valued network simplification using redundancy removal

# publications[].label
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Implementing Digital Logic with Sinusoidal Supplies

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accelerating Boolean Satisfiability on a Graphics Processing Unit

# publications[].label
Accelerating Statistical Static Timing Analysis Using Graphics Processing Units

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Alleviating NBTI-induced failure in off-chip output drivers

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Forbidden transition free crosstalk avoidance CODEC design

# publications[].label
A GPU-CPU heterogeneous algorithm for NGS read alignment

# publications[].label
VLSI implementation of a staggered sphere decoder design for MIMO detection

# publications[].label
Optimum Reverse Body Biasing for Leakage Minimization

# publications[].label
Simultaneous Input Vector Control and Circuit Modification

# publications[].label
Hardware Acceleration of Hash Operations in Modern Microprocessors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improving FPGA routability using network coding

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing.

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast, Ring-based Design of 3D Stacked DRAM

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Engineering change in a non-deterministic FSM setting

# publications[].label
Fault Table Generation using Graphics Processing Units

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Computation using noise-based logic: efficient string verification over a slow communication channel

# publications[].label
Modeling dynamic stability of SRAMs in the presence of single event upsets (SEUs)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
High-throughput VLSI implementations of iterative decoders and related code construction problems

# publications[].label
A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Noise-based Algorithms for Functional Equivalence and Tautology Checking

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Timing-Driven Decomposition of a Fast Barrel Shifter

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Process Variation Tolerant Single-supply True Voltage Level Shifter

# publications[].label
Efficient SAT-based Combinational ATPG using Multi-level Don't-Cares

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations

# publications[].label
A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A Timing-Driven Synthesis Approach of a Fast Four-Stage Hybrid Adder in Sum-of-Products

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks

# publications[].label
Analytical Determination of the Radiation-induced Pulse Shape

# publications[].label
Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations Introduction

# publications[].label
X-routing using two Manhattan route instances

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Binary and multi-valued SPFD-based wire removal in PLA networks

# publications[].label
Efficient Arithmetic Sum-of-Product (SOP) based Multiple Constant Multiplication (MCM) for FFT

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Exploring a Circuit Design Approach based on One-hot Multi-valued Domino Logic

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Study of composition schemes for mixed apply/compose based construction of ROBDDs

# publications[].label
A predictably low-leakage ASIC design style

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Novel Cryptographic Key Exchange Scheme using Resistors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A fast, analytical estimator for the SEU-induced pulse width in combinational designs

# publications[].label
A Fast, Source-synchronous Ring-based Network-on-Chip Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Computational evaluation of a novel beta radiation probe design using integrated circuits

# publications[].label
CMOS comparators for high-speed and low-power applications

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accelerating Boolean Satisfiability on a Custom IC

# publications[].label
Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities

# publications[].label
A Homomorphic Encryption Scheme Based on Affine Transforms

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An Efficient Approach to Sample On-Chip Power Supplies

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
IP routing table compression using ESPRESSO-MV

# publications[].label
Network coding for routability improvement in VLSI

# publications[].label
A structured ASIC design approach using pass transistor logic

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Inference of Gene Predictor Set Using Boolean Satisfiability

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Boolean satisfiability on a graphics processor

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A timing-driven hybrid-compression algorithm for faster sum-of-products

# publications[].label
GPU Acceleration for Bayesian Control of Markovian Genetic Regulatory Networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A PLA based asynchronous micropipelining approach for subthreshold circuit design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Multi-Valued Logic Crosstalk Avoidance Codes

# publications[].label
Adaptive Body Biasing to Compensate for PVT Variations

# publications[].label
An inversion-based synthesis approach for area and power efficient arithmetic sum-of-products

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Design of a Flash-based Circuit for Multi-valued Logic

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Modeling Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes

# publications[].label
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems

# publications[].label
Selective Forward Body Bias for High Speed and Low Power SRAMs

# publications[].label
A Ternary-valued, Floating Gate Transistor-based Circuit Design Approach

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Computing during supply voltage switching in DVS enabled real-time processors

# publications[].label
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

# publications[].publisher
Institution of Engineering and Technology (IET)

# publications[].label
Addressing the timing closure problem by integrating logic optimization and placement

# publications[].label
A design approach for radiation-hard digital electronics

# publications[].label
3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuit

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Exploiting Crosstalk to Speed up On-chip Buses

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Design and Implementation of a Sub-threshold BFSK Transmitter

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast, Ring-Based Design of 3-D Stacked DRAM

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Highly parallel decoding of space-time codes on graphics processing units

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Impedance matching techniques for VLSI packaging

# publications[].label
A Neutron Detector Using Integrated Circuits

# publications[].label
Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Package Construction and Electrical Modeling

# publications[].label
Controlling inductive cross-talk and power in off-chip buses using CODECs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Noise-based logic hyperspace with the superposition of 2(N) states in a single wire

# publications[].label
GPU implementation of a scalable non-linear congruential generator for cryptography applications

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Non-Manhattan routing using a Manhattan router

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Application of Logic Synthesis to the Understanding and Cure of Genetic Diseases

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A regularity-driven fast gridless detailed router for high frequency datapath designs

# publications[].label
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology

# publications[].label
An Algebraic Decision Diagram (ADD) based technique to find leakage histograms of combinational designs

# publications[].label
A merged synthesis technique for fast arithmetic blocks involving sum-of-products and shifters

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accelerating Fault Simulation Using Graphics Processors

# publications[].label
Leakage Reduction Techniques: Minimizing Leakage in Modern Day DSM Processes Conclusions and Future Directions

# publications[].label
Clamping Diode-based Radiation Tolerant Circuit Design Approach

# publications[].label
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Hardware Acceleration of EDA Algorithms, Custom ICs, FPGAs and GPUs

# publications[].label
A GPU-based Implementation of a Sensor Tasking Methodology

# publications[].label
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Novel VLSI layout fabric for deep sub-micron applications

# publications[].label
Noise-based Deterministic Logic and Computing: a Brief Survey

# publications[].label
A Plain-text Incremental Compression (PIC) Technique with Fast Lookup Ability

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Pipelined network of PLA based circuit design

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
GPU Architecture and the CUDA Programming Model

# publications[].label
3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits

# publications[].label
Efficient On-Chip Crosstalk Avoidance CODEC Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Exploring the Viability of Stochastic Computing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Architectural Simulations of a Fast, Source-Synchronous Ring-based Network-on-Chip Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Efficient don't care computation for hierarchical designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A robust algorithm for approximate Compatible Observability Don't Care (CODC) computation

# publications[].label
A PLL Design based on a Standing Wave Resonant Oscillator

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Low Power and High Performance SRAM Design using Bank-based Selective Forward Body Bias

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Boolean satisfiability using noise based logic

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
RF Receiver and Transmitter for Insect Mounted Sensor Platform

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Response to "Comment on 'Zero and negative energy dissipation at information-theoretic erasure'"

# publications[].label
CODEC Designs for Memoryless Crosstalk Avoidance Codes

# publications[].label
Automated Approach for Graphics Processor Based Software Acceleration

# publications[].label
Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits

# publications[].label
On and Off-Chip Crosstalk Avoidance in VLSI Design

# publications[].label
Resource sharing among mutually exclusive sum-of-product blocks for area reduction

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An Automated Approach for Minimum Jitter Buffered H - Tree Construction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Flash-based Digital Circuit Design Flow

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An Efficient and Regular Routing Methodology for Datapath Designs Using Net Regularity Extraction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A high-speed fully-programmable VLSI decoder for regular LDPC codes

# publications[].label
Polymeric Sensors to Monitor Cockroach Locomotion

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Synchronization of Ring-based Resonant Standing Wave Oscillators for 3D Clocking Applications

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fault Table Generation Using Graphics Processors

# publications[].label
FTCAM: An Area-Efficient Flash-Based Ternary CAM Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
SPFD-based wire removal in standard-cell and network-of-PLA circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Clock distribution scheme using coplanar transmission lines

# publications[].label
Network Coding for Routability Improvement in VLSI

# publications[].label
FPGA-Based Hardware Acceleration for Boolean Satisfiability

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Comparison of FinFET based FPGA LUT Designs

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An algorithm to minimize leakage through simultaneous input vector control and circuit modification

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Mixed Structural-Functional Path Delay Test Generation and Compaction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A delay-efficient radiation-hard digital design approach using CWSP elements

# publications[].label
A Robust Pulsed Flip-flop and its use in Enhanced Scan Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Methodology for Interconnect Dimension Determination

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Formal Verification of a Dynamic Multi-factor Secure Communication Protocol

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Boolean Satisfiability using Noise Based Logic

# publications[].label
A practical methodology to validate the statistical behavior of bloom filters

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Minimizing and Exploiting Leakage in VLSI Design Introduction

# publications[].label
A Low-jitter Phase-locked Resonant Clock Generation and Distribution Scheme

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
SAT-based ATPG using multilevel compatible don't-cares

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A fast ternary cam design for ip networking applications

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Implementing Low Power Digital Circuits using Flash Devices

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
On-chip Bidirectional Wiring for Heavily Pipe lined Systems using Network Coding

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Bus stuttering TB An encoding technique to reduce inductive noise in off-chip data transmission

# publications[].label
On Optimal and Achievable Fix-Free Codes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Critical Remarks on Landauer's principle of erasure-dissipation Including notes on Maxwell demons and Szilard engines

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Implementation of MOSFET based capacitors for digital applications

# publications[].label
Analysis and Avoidance of Cross-talk in On-Chip Buses

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accelerating Boolean Satisfiability on an FPGA

# publications[].label
Minimizing and Exploiting Leakage in VLSI Design

# publications[].label
Clock Distribution Scheme using Coplanar Transmission Lines

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast and Highly Scalable Bayesian MDP on a GPU Platform

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Efficient Analytical Determination of the SEU-induced Pulse Shape

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A timed automaton-based method for accurate computation of circuit delay in the presence of cross-talk

# publications[].label
A lithography-friendly structured ASIC design approach

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An Efficient, Scalable Hardware Engine for Boolean SATisfiability

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Look-up Table Design for Deep Sub-threshold through Full-supply Operation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Area-reducing sharing of mutually exclusive multiplier, MAC, adder and subtractor blocks

# publications[].label
Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG

# publications[].label
The HL Approach: A Low-Leakage ASIC Design Methodology

# publications[].label
Detection and Classification of Defects in XLPE Power Cable Insulation via Machine Learning Algorithms

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates

# publications[].label
Hardware Acceleration of EDA Algorithms Custom ICs, FPGAs and GPUs Conclusions

# publications[].label
Advanced Techniques in Logic Synthesis, Optimizations and Applications Introduction

# publications[].label
Exploring Static and Dynamic Flash-based FPGA Design Topologies

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Analysis and Design of Resilient VLSI Circuits, Mitigating Soft Errors and Process Variations

# publications[].label
Energy Efficient and High Speed On-Chip Ternary Bus

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A METAL and VIA maskset programmable VLSI design methodology using PLAs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router

# publications[].label
A Flash-based Digital to Analog Converter for Low Power Applications

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Probabilistic method to determine the minimum leakage vector for combinational designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A PLA based asynchronous micropipelining approach for subthreshold circuit design

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Analytical Model for Off-Chip Bus Performance

# publications[].label
Practical techniques to reduce skew and its variations in buffered clock networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An Area-efficient Ternary CAM Design using Floating Gate Transistors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An efficient pulse flip-flop based launch-on-shift scan cell

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A timing-driven approach to synthesize fast barrel shifters

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Logic Synthesis for Genetic Diseases, Modeling Disease Behavior Using Boolean Networks

# publications[].label
Techniques to Improve the Efficiency of SAT based Path Delay Test Generation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Toggle Equivalence Preserving (TEP) Logic Optimization

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A design flow to optimize circuit delay by using standard cells and PLAs

# publications[].label
Towards acceleration of fault simulation using Graphics Processing Units

# publications[].label
Encoding-based Minimization of Inductive Cross-talk for Off-chip Data Transmission

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Determining Gene Function in Boolean Networks using Boolean Satisfiability

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization

# publications[].label
Reclaiming the Sub-threshold Speed Penalty Through Micropipelining

# publications[].label
Zero and negative energy dissipation at information-theoretic erasure

# researcherOn[].label
Revolutionary Low Power Component Design for Man Portable Radiation Detectors

# researcherOn[].awardedBy.label
United States Department of Defense - (Washington D.C., District of Columbia, United States)

# researcherOn[].label
RTML: Small: Real-Time Model-Based Bayesian Reinforcement Learning

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].label
PFI-AIR-TT: Wearable Sleepwear for Quantitative Prognostication and Noninvasive Therapy of Obstructive Sleep Apnea

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# streetAddress
Texas A&M University; Electrical Engineering; 3128 TAMU

# etdChairOf[].label
Ekambavanan, Sasidharan (2009-05). Encoding serial data for energy-delay-product and energy minimization. Master's Thesis.

# etdChairOf[].label
Poothamkurissi Swaminathan, Subramanian (2012-08). Timing Aware Partitioning for Multi-FPGA based Logic Simulation using Top-down Selective Flattening. Master's Thesis.

# etdChairOf[].label
Garg, Rajesh (2003-05). Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares. Master's Thesis.

# etdChairOf[].label
Karkala, Vinay (2010-08). A PLL Design Based on a Standing Wave Resonant Oscillator. Master's Thesis.

# etdChairOf[].label
Jayakumar, Nikhil (2007-05). Minimizing and exploiting leakage in VLSI. Doctoral Dissertation.

# etdChairOf[].label
Kumar, Rajeev (2013-04). An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT. Master's Thesis.

# etdChairOf[].label
Cobb, Jeffrey Lee (2009-05). A robust window-based multi-node minimization technique using Boolean relations. Master's Thesis.

# etdChairOf[].label
Gulati, Kanupriya (2009-12). Hardware Acceleration of Electronic Design Automation Algorithms. Doctoral Dissertation.

# etdChairOf[].label
Kumar, Harsh (2016-12). A Plain-text Compression Technique with Fast Lookup Ability. Master's Thesis.

# etdChairOf[].label
Garg, Rajesh (2009-05). Analysis and Design of Resilient VLSI Circuits. Doctoral Dissertation.

# etdChairOf[].label
Mandal, Ayan (2013-05). Efficient Design and Clocking for a Network-on-Chip. Doctoral Dissertation.

# etdChairOf[].label
Paul, Suganth (2007-12). Design and implementation of a sub-threshold wireless BFSK transmitter. Master's Thesis.

# etdChairOf[].label
Bian, Kun (2013-12). Efficient Path Delay Test Generation with Boolean Satisfiability. Doctoral Dissertation.

# etdChairOf[].label
Singh, Karandeep (2003-05). Maximum and minimum sensitizable timing analysis using data dependent delays. Master's Thesis.

# etdChairOf[].label
Murray, Luke (2014-12). Efficient On-Chip Power Supply Sampling to Improve Post-Silicon Debug. Master's Thesis.

# etdChairOf[].label
Gulati, Kanupriya (2003-05). Computing leakage current distributions and determination of minimum leakage vectors for combinational designs. Master's Thesis.

# etdChairOf[].label
Lin, Pey Chang K (2013-08). Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks. Doctoral Dissertation.

# etdChairOf[].label
Elshennawy, Amr (2014-12). An Asynchronous Network-On-Chip Router with Low Standby Power. Master's Thesis.

# etdChairOf[].label
Nagpal, Charu (2008-10). A delay-efficient radiation-hard digital design approach using code word state preserving (cwsp) elements. Master's Thesis.

# etdChairOf[].label
Bollapalli, Kalyana Chakravarthy (2009-12). IP Routing Table Compression Using TCAM and Distance-one Merge. Master's Thesis.

# etdChairOf[].label
Kumar, Rajesh (2010-08). A Radiation Tolerant Phase Locked Loop Design for Digital Electronics. Master's Thesis.