# overview
My research interests include fault-tolerance, verification simulation, high-performance VLSI circuits, radiation testing, design for dependability and software engineering.

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# educationAndTraining[].organization.label
University of Illinois at Urbana Champaign - (Urbana, Illinois, United States)

# awardsAndHonors[].label
Faculty Early Career Development (CAREER) Program

# publications[].label
ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation*

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency

# publications[].label
Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Low-density parity-check decoder architecture for high throughput optical fiber channels

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A high-throughput multimode low-density parity-check decoder for 5G New Radio

# publications[].label
Decoding of quasi-cyclic LDPC codes using an on-the-fly computation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A gate-level simulation environment for alpha-particle-induced transient faults

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A massively scaleable decoder architecture for low-density parity-check codes

# publications[].label
Architecture for Reconfigurable MIMO Detector and its FPGA Implementation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Next Generation Iterative LDPC Solutions for Magnetic Recording Storage

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A High-Throughput Multi-Mode LDPC Decoder for 5G NR

# publications[].label
Low density parity check decoder for regular LDPC codes

# publications[].label
Asynchronous Baseband Processor Design for Cooperative MIMO Satellite Communication

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Signal Reconstruction Processor Design For Compressive Sensing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
WaveSync: A low-latency source synchronous bypass network-on-chip architecture

# publications[].label
Low-Power Embedded LDPC-H.264 Joint Decoding Architecture Based on Unequal Error Protection

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Compressive Sensing and Reception for MIMO-OFDM Based Cognitive Radio

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A parallel VLSI architecture for layered decoding for array LDPC codes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Optimization of thermoelectric system for pavement energy harvesting

# publications[].label
Fault behavior dictionary for simulation of device-level transients

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A design approach for radiation-hard digital electronics

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
SEU Hardened Clock Regeneration Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Diagonal Low-Density Parity-Check code for simplified routing in decoder

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Support Vector Machine Based Detection of Drowsiness Using Minimum EEG Features

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
FOCUS: an experimental environment for validation of fault-tolerant systems-case study of a jet-engine controller

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Quasi-model-independent search for new high p(T) physics at D0.

# publications[].label
Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Low-Power On-the-Fly Reconfigurable Iterative MIMO Detection and LDPC Decoding Design

# publications[].label
XJ-BP: Express Journey Belief Propagation Decoding for Polar Codes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast simulation technique for LDPC code analysis

# publications[].label
Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels

# publications[].label
Overlapped List Successive Cancellation Approach for Hardware Efficient Polar Code Decoder

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Systolic like soft-detection architecture for 4x4 64-QAM MIMO system

# publications[].label
Minimum-Energy LDPC Decoder for Real-Time Mobile Application

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Low density parity check decoder for irregular LDPC codes

# publications[].label
Timing Failure Analysis of Commercial CPUs Under Operating Stress

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A reliability testing environment for off-the-shelf memory subsystems

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An LDPC Decoding Schedule for Memory Access Reduction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Scaleable check node centric architecture for LDPC decoder

# publications[].label
Wear-out simulation environment for VLSI designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Information theoretic capacity of long on-chip interconnects in the presence of crosstalk

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
High Performance On the Fly Reconfigurable MIMO Detector

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Data Handling Limits of On-Chip Interconnects

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A high-speed fully-programmable VLSI decoder for regular LDPC codes

# publications[].label
Asynchronous Bypass Channels: Improving Performance for Multi-Synchronous NoCs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Simulated fault injection: a methodology to evaluate fault tolerant microprocessor architectures

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
VLSI architectures for layered decoding for irregular LDPC codes of WiMax

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Data Processing Logic for Stacked Wafer-Scale CMOS Radiation Sensor Network

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An FPGA Implementation of Dirty Paper Precoder

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Simulation using code-perturbation: Black- and white-box approach

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An Iterative LR-Aided MMSE Extended Soft MIMO Decoding Algorithm

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Low density parity check decoder for irregular LDPC codes

# publications[].label
Low density parity check decoder for regular LDPC codes

# publications[].label
An Iterative Soft Decision Based Adaptive K-best Decoder without SNR Estimation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Si-emulation: System verification using simulation and emulation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Tiling Parity-Check Matrix for Reduced Complexity High Throughput Low-Density Parity-Check Decoders

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Speculative Energy Scheduling for LDPC Decoding

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Low-Power Preamble Detection Methodology for Packet Based RF Modems on All-Digital Sensor Front-Ends

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
VLSI implementation of a staggered sphere decoder design for MIMO detection

# publications[].label
Low-Power Baseband Processing for Wireless Multimedia Systems using Unequal Error Protection

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Low-Power, Resilient Interconnection with Orthogonal Latin Squares

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Quantized LDPC decoder design for binary symmetric channels

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
RTL Functional Verification Using Excitation and Observation Coverage

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
TC: Throughput Centric Successive Cancellation Decoder Hardware Implementation for Polar Codes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-path NoC Router

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
K-Best Decoders for 5G+ Wireless Communication

# publications[].label
Array Like Runtime Reconfigurable MIMO Detectors for 802.11n WLAN: A Design Case Study

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Search for large extra dimensions in dielectron and diphoton production.

# publications[].label
Fpga Based Implementation of Decoder for Array Low-Density Parity-Check Codes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Bidirectional Interconnect Design for Low Latency High Bandwidth NoC

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A fast and accurate gate-level transient fault simulation environment

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# researcherOn[].label
Collaborative Research: Advanced Coding Techniques for Next-Generation Optical Communications

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# streetAddress
Texas A&M University; Electrical Engineering; 3128 TAMU

# etdChairOf[].label
Wang, Qian (2016-08). Architectures and Design of VLSI Machine Learning Systems. Doctoral Dissertation.

# etdChairOf[].label
Selvarathinam, Anand Manivannan (2005-11). High throughput low power decoder architectures for low density parity check codes. Doctoral Dissertation.

# etdChairOf[].label
Deshpande, Hrishikesh (2012-05). Multipath Router Architectures to Reduce Latency in Network-on-Chips. Master's Thesis.

# etdChairOf[].label
Bhagawat, Pankaj (2012-02). Hardware Accelerator for MIMO Wireless Systems. Doctoral Dissertation.

# etdChairOf[].label
Arya, Richeek (2012-10). Soft MIMO Detection on Graphics Processing Units and Performance Study of Iterative MIMO Decoding. Master's Thesis.

# etdChairOf[].label
Pu, Lingjun (2015-08). A Software Defined Radio Experimental Platform for GPS/GNSS Signal Reception Analysis. Master's Thesis.

# etdChairOf[].label
Wang, Weihuang (2009-05). Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. Master's Thesis.

# etdChairOf[].label
Okorafor, Ekpe Apia (2007-04). Design and analysis of a 3-dimensional cluster multicomputer architecture using optical interconnection for petaFLOP computing. Doctoral Dissertation.

# etdChairOf[].label
Kumar, Reeshav (2011-08). Communication Reliability in Network on Chip Designs. Master's Thesis.

# etdChairOf[].label
Chang, Sanghoan (2009-05). Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy. Doctoral Dissertation.

# etdChairOf[].label
Singhal, Rohit (2007-09). Data integrity for on-chip interconnects. Doctoral Dissertation.

# etdChairOf[].label
Tamilarasan, Karthik Prabhu (2012-02). Built-In Self Test (BIST) for Realistic Delay Defects. Master's Thesis.

# etdChairOf[].label
Kumar, Poornachandran (2010-08). Efficient Lookahead Routing and Header Compression For Multicasting in Networks-On-Chip. Master's Thesis.

# etdChairOf[].label
Dash, Rajballav (2009-12). VLSI Implementation of Low Power Reconfigurable MIMO Detector. Master's Thesis.

# etdChairOf[].label
Gunnam, Kiran Kumar (2009-05). Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation. Doctoral Dissertation.

# etdChairOf[].label
Gao, Di (2015-11). Multi-harmonic Modeling of Low-power PWM DC-DC Converter. Master's Thesis.

# etdChairOf[].label
Vageesan, Gopinath (2007-04). On improving performance and conserving power in cluster-based web servers. Master's Thesis.

# etdChairOf[].label
Yu, Shaoda (2014-08). EEG-based Drowsiness Detection using Support Vector Machine. Master's Thesis.