# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4.1 Discovery And Preclinical Testing Of Markers And Technologies

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4.1 Discovery And Preclinical Testing Of Markers And Technologies

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
Automatic Test Pattern Generation (atpg)

# keywords[]
4.1 Discovery And Preclinical Testing Of Markers And Technologies

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
Stem Cell Research - Nonembryonic - Non-human

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# educationAndTraining[].organization.label
California Institute of Technology - (Pasadena, California, United States)

# educationAndTraining[].organization.label
Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States)

# educationAndTraining[].organization.label
Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States)

# publications[].label
Challenges in Delay Testing of Integrated Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Immediate neighbor difference I-DDQ test (INDIT) for outlier identification

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
CodSim - A combined delay fault simulator

# publications[].label
Model-based I-DDQ pass/fail limit setting

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise

# publications[].label
K longest paths per gate (KLPG) test generation for scan-based sequential circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Design for Yield and Reliability is MORE Important Than DFT

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accurate yield estimation of circuits with redundancy

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
I<inf>DDQ</inf>testing of input/output resources of SRAM-based FPGAs

# publications[].label
A circuit level fault model for resistive bridges

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Evaluation of effectiveness of median of absolute deviations outlier rejection-based I-DDQ testing for burn-in reduction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Statistical Fault Coverage Metric for Realistic Path Delay Faults

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
I-DDQ test: Will it survive the DSM challenge?

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A circuit level fault model for resistive opens and bridges

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Cable modem at home - The author responds

# publications[].label
Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Comparison of wafer-level spatial I-DDQ estimation methods: NNR versus NCR

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Simulation-based design error diagnosis and correction in combinational digital circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Impact of Test Compression on Power Supply Noise Control

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
DVLASIC - CATASTROPHIC FAULT YIELD SIMULATION IN A DISTRIBUTED-PROCESSING ENVIRONMENT

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Dynamic compaction for high quality delay test

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A statistical fault coverage metric for realistic path delay faults

# publications[].label
PARADE: PARAmetric delay evaluation under process variation

# publications[].label
Timing analysis of combinational circuits including capacitive coupling and statistical process variation

# publications[].label
Static compaction of delay tests considering power supply noise

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Is I-DDQ test of microprocessors feasible?

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Vector-Based Approach for Power Supply Noise Analysis in Test Compaction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations

# publications[].label
Longest path selection for delay test under process variation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Key attributes of an SRAM testing strategy required for effective process monitoring

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Pseudo Functional Path Delay Test through Embedded Memories

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A TCAD Framework for Development and Manufacturing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accurate fault modeling and fault simulation of resistive bridges

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Maximizing Crosstalk-Induced Slowdown during Path Delay Test

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
PARADE: PARAmetric Delay Evaluation Under Process Variation **This research was supported in part by the SRC grant 000-TJ-844, NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001.

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Yield analysis for fault-tolerant arrays.

# publications[].label
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A fast algorithm for critical path tracing in VLSI digital circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
I-DDQ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Yield learning model for integrated circuit package assembly

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Requirements for practical I-DDQ testing of deep submicron circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
IC performance prediction for test cost reduction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Built-In Proactive Tuning System for Circuit Aging Resilience

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Chip level power supply partitioning for I-DDQ testing using built-in current sensors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Optimal voltage testing for physically-based faults

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Mixed Structural-Functional Path Delay Test Generation and Compaction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Technology Scaling Issues of an IDDQ Built-In Current Sensor

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Yield learning in integrated circuit package assembly

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A SEMICONDUCTOR WAFER REPRESENTATION DATABASE AND ITS USE IN THE PREDATOR PROCESS EDITOR AND STATISTICAL SIMULATOR

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
IC outlier identification using multiple test metrics

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Levelized Low Cost Delay Test Compaction Considering IR-Drop Induced Power Supply Noise

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Neighbor current ratio (NCR): A new metric for I-DDQ data analysis

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Comparison of NCR effectiveness with a reduced I-DDQ vector set

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
CodSim - A combined delay fault simulator

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
NCR: A self-scaling, self-calibrated metric for I-DDQ outlier identification

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
At-speed test for path delay faults using practical techniques

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Use of multiple I-DDQ test metrics for Outlier identification

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
HIERARCHICAL MAPPING OF SPOT DEFECTS TO CATASTROPHIC FAULTS - DESIGN AND APPLICATIONS

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
PROBE: a PPSFP simulator for resistive bridging faults

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
CROWNE: Current Ratio outliers with neighbor estimator

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Modeling power supply noise in delay testing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Topological Heuristics for Scan Test Overhead Reduction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
THE CDB HCDB SEMICONDUCTOR WAFER REPRESENTATION SERVER

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Chip level power supply partitioning for I<inf>DDQ</inf> testing using built-in current sensors

# publications[].label
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
I-DDQ data analysis using neighbor current ratios

# publications[].label
Soft-programmable bypass switch design for defect-tolerant arrays

# publications[].label
SOFT-PROGRAMMABLE BYPASS SWITCH DESIGN FOR DEFECT-TOLERANT ARRAYS

# publications[].label
Contamination control using production test data

# publications[].label
Resistive bridge fault modeling, simulation and test generation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Yield Simulation for Integrated Circuits

# publications[].label
IDDQ Test Using Built-In Current Sensing of Supply Line Voltage Drop

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Defect localization using physical design and electrical test information

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Estimation of reject ratio in testing of combinatorial circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Reliable Energy Efficient Routing in Wireless Sensor Networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Testing the path delay faults of ISCAS85 circuit c6288

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

# publications[].label
Improved Power Supply Noise Control for Pseudo Functional Test

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Bridging fault detection in FPGA interconnects using I<inf>DDQ</inf>

# publications[].label
A practical built-in current sensor for I-DDQ testing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Application of defect simulation as a tool for more efficient failure analysis

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fault probability prediction for array based designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A circuit level fault model for resistive shorts of MOS gate oxide

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
SEMICONDUCTOR WAFER REPRESENTATION FOR TCAD

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An efficient solution to the storage correspondence problem for large sequential circuits

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
CROWNE: Current ratio outliers with neighbor estimator

# publications[].label
TEST QUALITY AND YIELD ANALYSIS USING THE DEFAM DEFECT TO FAULT MAPPER

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Test quality and yield analysis using the DEFAM defect to fault mapper

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improvement of SRAM-based failure analysis using calibrated Iddq testing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Techniques to Improve the Efficiency of SAT based Path Delay Test Generation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Estimation of fault-free leakage current using wafer-level spatial information

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Comparison of effectiveness of current ratio and delta-I-DDQ tests

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
System and method for detecting quiescent current in an integrated circuit

# publications[].label
ARCHITECTURES FOR CATASTROPHIC AND DELAY FAULT-TOLERANCE

# publications[].label
Longest-path selection for delay test under process variation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit

# publications[].label
An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit

# publications[].label
Detection of bridging faults in logic resources of configurable FPGAs using I-DDQ

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improved wafer-level spatial analysis for I-DDQ limit setting

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Power Supply Noise Control in Pseudo Functional Test

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# researcherOn[].label
A Computer-based, Student-Centered Middle-School Approach to One Health Learning

# researcherOn[].awardedBy.label
National Institutes of Health - (Bethesda, Maryland, United States)

# researcherOn[].awardedBy.preferredLabel
DHHS-NIH-National Institute of General Medical Science

# researcherOn[].label
FFATA: SHF: Small: High Quality Test and Post-Silicon Validation of System-On-Chip Integrated Circuits

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# streetAddress
Texas A&M University; Computer Science & Engineering; 3112 TAMU

# etdChairOf[].label
Prasad, Abhijit (2003-12). Power supply partitioning for placement of built-in current sensors for IDDQ testing. Master's Thesis.

# etdChairOf[].label
Wu, Lei (2007-12). An efficient logic fault diagnosis framework based on effect-cause approach. Doctoral Dissertation.

# etdChairOf[].label
Gharaibeh, Ammar (2010-01). A Behavioral Model of a Built-in Current Sensor for IDDQ Testing. Master's Thesis.

# etdChairOf[].label
Tamilarasan, Karthik Prabhu (2012-02). Built-In Self Test (BIST) for Realistic Delay Defects. Master's Thesis.

# etdChairOf[].label
Wang, Jing (2007-08). Power supply noise in delay testing. Doctoral Dissertation.

# etdChairOf[].label
Gao, Yukun (2015-05). Pseudo Functional Path Delay Test through Embedded Memories. Master's Thesis.

# etdChairOf[].label
Jung, Eun Jae (2007-12). Creation and maintenance of a communication tree in wireless sensor networks. Doctoral Dissertation.

# etdChairOf[].label
Sabade, Sagar Suresh (2005-05). Integrated circuit outlier identification by multiple parameter correlation. Doctoral Dissertation.

# etdChairOf[].label
Parikh, Shaishav Shailesh (2005-08). Testing tri-state and pass transistor circuit structures. Master's Thesis.

# etdChairOf[].label
Wang, Zheng (2010-05). High Quality Compact Delay Test Generation. Doctoral Dissertation.

# etdChairOf[].label
Chakraborty, Avijit (2015-11). Observability Driven Path Generation for Delay Test. Master's Thesis.

# etdChairOf[].label
Chakraborty, Swati (2015-05). At-Speed Path Delay Test. Master's Thesis.

# etdChairOf[].label
Yang, Xu (2009-05). On the development of Voice over IP. Doctoral Dissertation.

# etdChairOf[].label
Balasubramanian, Vijay (2006-12). Variance reduction and outlier identification for IDDQ testing of integrated chips using principal component analysis. Master's Thesis.

# etdChairOf[].label
Jiang, Zhongwei (2010-12). Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits. Doctoral Dissertation.

# etdChairOf[].label
Zhang, Tengteng (2015-12). High Quality Test Generation Targeting Power Supply Noise. Doctoral Dissertation.

# etdChairOf[].label
Lahiri, Shayak (2011-12). Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing. Master's Thesis.

# etdChairOf[].label
Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform. Master's Thesis.

# etdChairOf[].label
Bian, Kun (2013-12). Efficient Path Delay Test Generation with Boolean Satisfiability. Doctoral Dissertation.

# etdChairOf[].label
Boga, Viswanath (2016-05). Optimization of Pseudo Functional Path Delay Test Through Embedded Memories. Master's Thesis.

# etdChairOf[].label
Biswas, Prasenjit (2016-08). Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. Master's Thesis.

# etdChairOf[].label
Kim, Hyun Sung (2007-08). Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. Master's Thesis.

# etdChairOf[].label
Gope, Dibakar (2012-10). Maximizing Crosstalk-Induced Slowdown During Path Delay Test. Master's Thesis.

# etdChairOf[].label
Qiu, Wangqi (2007-04). Fault simulation and test generation for small delay faults. Doctoral Dissertation.

# etdChairOf[].label
Veluswami, Senthilkumar (2005-08). Statistical static timing analysis considering process variations and crosstalk. Master's Thesis.

# etdChairOf[].label
Xue, Bin (2005-12). Voltage sensing based built-in current sensor for IDDQ test. Doctoral Dissertation.

# etdChairOf[].label
Gill, Arjun (2013-05). Optimizing Test Pattern Generation Using Top-Off ATPG Methodology for Stuck–AT, Transition and Small Delay Defect Faults. Master's Thesis.

# etdChairOf[].label
Pokharel, Punj (2013-08). Path Delay Test Through Memory Arrays. Master's Thesis.