# positions[].organizations[].parent[].label
Texas A&M Engineering Experiment Station (TEES)

# overview
Current research: optimization for energy-efficient VLSI circuits, on-chip communication fabrics, dynamic power management, adaptive circuit design, interactions between physical design and system-level design, heuristics for large scale combinatorial optimization.

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
Stem Cell Research - Nonembryonic - Non-human

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
General-purpose Graphics Computing Unit (gpgpu)

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
Dynamic Voltage Frequency Scaling (dvfs)

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# educationAndTraining[].organization.label
University of Minnesota - (Minneapolis, Minnesota, United States)

# educationAndTraining[].organization.label
Zhejiang University - (Hangzhou, Zhejiang, China)

# educationAndTraining[].organization.label
Zhejiang University - (Hangzhou, Zhejiang, China)

# publications[].label
Combinatorial Algorithms for Fast Clock Mesh Optimization* *This work was supported in part by SRC under contract number 2004-TJ-1205 and 2006-TJ-1416.

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A survey on multi-net global routing for integrated circuits

# publications[].label
An improved AMG-based method for fast power grid analysis

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accurate Estimation of Global Buffer Delay within a Floorplan

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Buffering Interconnect for Multicore Processor Designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Having Your Cake and Eating It Too: Energy Savings without Performance Loss through Resource Sharing Driven Power Management

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Bound for unwanted clock skew due to wire width variation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
High performance clock routing in X-architecture

# publications[].label
Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI interconnect under a higher order AWE model

# publications[].label
Buffer insertion with adaptive blockage avoidance

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Buffered clock tree for high quality IC design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Pre-search Assisted ILP Approach to Analog Integrated Circuit Routing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Joint Precision Optimization and High Level Synthesis for Approximate Computing

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
FAR-DS: Full-plane AWE Routing with Driver Sizing

# publications[].label
A single layer zero skew clock routing in X architecture

# publications[].label
Multi-Scenario Buffer Insertion in Multi-Core Processor Designs

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
The Cat and Mouse in Split Manufacturing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improved algorithms for link-based non-tree Clock Networks for skew variability reduction

# publications[].label
Making Split Fabrication Synergistically Secure and Manufacturable

# publications[].label
Reducing clock Skew variability via cross links

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Coupling aware timing optimization and antenna avoidance in layer assignment

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Special Section on the 2011 International Symposium on Physical Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Optimal Design of JPEG Hardware Under the Approximate Computing Paradigm

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Power grid analysis and optimization using algebraic multigrid

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Algorithms for Power-Efficient QoS in Application Specific NoCs

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Special Issue on the 2006 International Symposium on Physical Design

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A new fast slew buffering algorithm without input slew assumptions

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Register placement for low power clock network

# publications[].label
Accurate clock mesh sizing via sequential quadraticprogramming

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Non-Hanan Optimization for Global VLSI Interconnect

# publications[].label
Proceedings of the International Symposium on Physical Design: Foreword

# publications[].label
Soft clock skew scheduling for variation-tolerant signal processing circuits: A case study of viterbi decoders

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
The Cat and Mouse in Split Manufacturing

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
GPU-Based Parallel Computing for Fast Circuit Optimization

# publications[].label
GPU Acceleration for Bayesian Control of Markovian Genetic Regulatory Networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
ASIC design flow considering lithography-induced effects

# publications[].publisher
Institution of Engineering and Technology (IET)

# publications[].label
Performance Driven Global Routing Through Gradual Refinement

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Impact of Lithography-friendly Circuit Layout

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Applications of Network Coding in Global Routing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Gate Sizing for Cell-Library-Based Designs

# publications[].label
Efficient Rerouting Algorithms for Congestion Mitigation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Special Section on Physical Design Techniques for Advanced Technology Nodes

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Gate Sizing for Cell-Library-Based Designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A placement methodology for robust clocking

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Statistical clock tree routing for robustness to process variations

# publications[].label
Steiner network construction for timing critical nets

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Timing Verification for Adaptive Integrated Circuits

# publications[].label
Built-In Self Optimization for Variation Resilience of Analog Filters

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Gate sizing for cell library-based designs

# publications[].label
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Navigating register placement for low power clock network design

# publications[].publisher
Institute of Electronics, Information and Communications Engineers (IEICE)

# publications[].label
Buffer insertion with adaptive blockage avoidance

# publications[].label
Elastic Timing Scheme for Energy-Efficient and Robust Performance

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Making fast buffer insertion even faster via approximation techniques

# publications[].label
A global minimum clock distribution network augmentation algorithm for guaranteed clock skew yield

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A practical methodology for early buffer and wire resource allocation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Low power gated clock tree driven placement

# publications[].publisher
Institute of Electronics, Information and Communications Engineers (IEICE)

# publications[].label
Case Studies on Variation Tolerant and Low Power Design using Planar Asymmetric Double Gate Transistor

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Wire sizing and spacing for lithographic printability optimization

# publications[].publisher
SPIE, the international society for optics and photonics

# publications[].label
A practical methodology for early buffer and wire resource allocation

# publications[].label
Proximity Sensing Based on a Dynamic Vision Sensor for Mobile Devices

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast algorithms for slew constrained minimum cost buffering

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Clock Buffer Polarity Assignment for Power Noise Reduction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Accelerating Clock Mesh Simulation Using MatrixLevel Macromodels and Dynamic Time Step Rounding

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Integrated placement and skew optimization for rotary clocking

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Performance driven global routing through gradual refinement

# publications[].label
Associative skew clock routing for difficult instances

# publications[].label
A new algorithm for simultaneous gate sizing and threshold voltage assignment

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Transient and Fine-Grained Voltage Adaptation for Variation Resilience in VLSI Interconnects

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Efficient model update for general link-insertion networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast and flexible buffer trees that navigate the physical layout environment

# publications[].label
Gate Sizing and Device Technology Selection Algorithms for High-Performance Industrial Designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Methodology for the Simultaneous Design of Supply and Signal Networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Special Section on Cross-Domain Physical Optimization

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Built-In Proactive Tuning System for Circuit Aging Resilience

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Special Issue on the 57th International Midwest Symposium on Circuits and Systems

# publications[].label
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
GPU-Based Parallelization for Fast Circuit Optimization

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Steiner Tree Optimization for Buffers, Blockages, and Bays

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
SAT Based Multi-Net Rip-up-and-Reroute for Manufacturing Hotspot Removal

# publications[].label
Handling Partial Correlations in Yield Prediction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A timing-constrained simultaneous global routing algorithm

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Power Gating with Block Migration in Chip-Multiprocessor Last-Level Caches

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Buffered Steiner trees for difficult instances

# publications[].label
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Exploiting level sensitive latches in wire pipelining

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Dual-Level Adaptive Supply Voltage System for Variation Resilience

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Low Overhead Built-In Delay Testing with Voltage and Frequency Adaptation for Variation Resilience

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Resource Allocation Algorithms for Guaranteed Service in Application-Specific NoCs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
GPU Acceleration for PCA-Based Statistical Static Timing Analysis

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A Built-In Self-Test and <italic>In Situ</italic> Analog Circuit Optimization Platform

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Efficient CongestionMitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

# publications[].label
Simultaneous Technology Mapping and Placement for Delay Minimization

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Lagrangian Relaxation for Gate Implementation Selection

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Accurate estimation of global buffer delay within a floorplan

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Dynamic voltage and frequency scaling for shared resources in multicore processor designs

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A fast general slew constrained minimum cost buffering algorithm

# publications[].label
Low Power Clock Buffer Planning Methodology in F-D Placement for Large Scale Circuit Design*This work was supported partly by National Science Foundation of China (90407005, 90607001 and 60776026), and project of 3-D floorplanning and placement of Intel Corporation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Practical techniques to reduce skew and its variations in buffered clock networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A simple yet effective merging scheme for prescribed-skew clock routing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Process variation aware clock tree routing

# publications[].label
Combinatorial Algorithms for Fast Clock Mesh Optimization

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Collaborative Gate Implementation Selection and Adaptivity Assignment for Robust Combinational Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
RouteNet: Routability Prediction for Mixed -Size Designs Using Convolutional Neural Network

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Modeling, Optimization and Control of Rotary Traveling-Wave Oscillator

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An efficient alorintham for RLC buffer insertion

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Physical Design Techniques for Optimizing RTA-induced Variations

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Integrated placement and skew optimization for rotary clocking

# publications[].label
An efficient merging scheme for prescribed skew clock routing

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

# publications[].label
Analytical bound for unwanted clock skew due to wire width variation

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Special Issue on Genomic Signal Processing FOREWORD

# publications[].label
Exploring Serverless Computing for Neural Network Training

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Steiner tree optimization for buffers. Blockages and bays

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Layout modification for library cell Alt-PSM composability

# publications[].publisher
SPIE, the international society for optics and photonics

# publications[].label
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast algorithms for slew-constrained minimum cost buffering

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Unified adaptivity optimization of clock and logic signals

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Porosity aware buffered steiner tree construction

# publications[].label
Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Up By Their Bootstraps: Online Learning in Artificial Neural Networks for CMP Uncore Power Management

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An Analytical Approach for Error PMF Characterization in Approximate Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Navigating registers in placement for clock network minimization

# publications[].label
Clock Buffer Polarity Assignment for Power Noise Reduction**This work is partially supported by Semiconductor Research Corporation under contract 2004-TJ-1205.

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Control Synthesis and Delay Sensor Deployment for Efficient ASV Designs

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Dual-Level Adaptive Supply Voltage System for Variation Resilience

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Library cell layout with Alt-PSM compliance and composability

# publications[].label
A timing-constrained algorithm for simultaneous global routing of multiple nets

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A place and route aware buffered steiner tree construction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Useful Clock Skew Optimization under A Multi-corner Multi-mode Design Framework

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Boostable Repeater Design for Variation Resilience in VLSI Interconnects

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Layer assignment for crosstalk risk minimization

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Proximity Optimization for Adaptive Circuit Design

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Skew scheduling and clock routing for improved tolerance to process variations

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Robust clock tree routing in the presence of process variations

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Buffered Steiner Trees for Difficult Instances

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Congestion-Driven Codesign of Power and Signal Networks **This work was supported in part by the NSF under award CCR-0098117 and by the SRC under contract 99-TJ-714.

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Wire sizing and spacing for lithographic printability and timing optimization

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Utilizing redundancy for timing critical interconnect

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast Decap Allocation Based on Algebraic Multigrid

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Detecting Tangled Logic Structures in VLSI Netlists

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Discrete Buffer and Wire Sizing for Link-based Non-tree Clock Networks

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstacles

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Clock network minimization methodology based on incremental placement

# publications[].label
Reducing clock skew variability via crosslinks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Making Split Fabrication Synergistically Secure and Manufacturable

# publications[].label
DiCER: Distributed and cost-effective redundancy for variation tolerance

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
GPU-based parallelization for fast circuit optimization

# publications[].label
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles

# researcherOn[].label
SHF:Small: OSCARS:  Optimizing Self-Configurable Analog ICs for Reliability and Security

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].label
RTML: Small: Real-Time Model-Based Bayesian Reinforcement Learning

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].label
STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].label
CPS: Medium: Real-Time Learning and Control of Stochastic Nanostructure Growth Processes Through in situ Dynamic Imaging

# researcherOn[].awardedBy.label
Directorate for Engineering - (Arlington, Virginia, United States)

# researcherOn[].label
Design Automation for Cost-Effective Implementation of Adaptive Integrated Circuits

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# streetAddress
Texas A&M University; Electrical Engineering; 3128 TAMU

# organizations[]
Texas A&M Engineering Experiment Station (TEES)

# schools[]
Texas A&M Engineering Experiment Station (TEES)

# etdChairOf[].label
Chang, Chi-Yu (2012-08). Analytical Layer Planning for Nanometer VLSI Designs. Master's Thesis.

# etdChairOf[].label
Chen, Xi (2013-05). Physical Planning and Uncore Power Management for Multi-Core Processors. Doctoral Dissertation.

# etdChairOf[].label
Rasheed, Shalimar (2014-05). A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. Master's Thesis.

# etdChairOf[].label
Puli, Ramprakash Reddy (2018-05). Active Routing: Compute on the Way for Near-Data Processing. Master's Thesis.

# etdChairOf[].label
Lu, Ang (2015-12). Proximity Optimization for Adaptive Circuit Design. Master's Thesis.

# etdChairOf[].label
Sun, Lijia (2018-08). Modeling and Control Techniques in Smart Systems. Doctoral Dissertation.

# etdChairOf[].label
Zhai, Sitong (2015-08). A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks. Master's Thesis.

# etdChairOf[].label
Tsai, Jung-Tai (2013-08). VLSI Interconnect Optimization Considering Non-uniform Metal Stacks. Master's Thesis.

# etdChairOf[].label
Wu, Chia-Yu (2015-08). A Pre-Search Assisted ILP Approach to Analog Integrated Circuit Routing. Master's Thesis.

# etdChairOf[].label
Kumar, Rohit (2014-08). Timing Verification of Adaptive Integrated Circuits. Master's Thesis.

# etdChairOf[].label
Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform. Master's Thesis.

# etdChairOf[].label
Gope, Dibakar (2011-08). Maximizing Crosstalk-Induced Slowdown During Path Delay Test. Master's Thesis.

# etdChairOf[].label
Kansal, Rohan (2013-08). A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects. Master's Thesis.

# etdChairOf[].label
Xu, Zheng (2013-08). Control Techniques for Uncore Power Mangement in Chip Multiprocessor Designs. Master's Thesis.

# etdChairOf[].label
Shen, Yiren (2016-05). Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits. Master's Thesis.

# etdChairOf[].label
Huang, Yi-Le (2010-12). An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization. Master's Thesis.

# etdChairOf[].label
Gao, Zhuoyang (2015-12). Comparative Study on Performance and Variation Tolerance of Low Power Circuit. Master's Thesis.

# etdChairOf[].label
Zhao, Qiong (2012-05). Track Assignment Considering Crosstalk-Induced Performance Degradation. Master's Thesis.

# etdChairOf[].label
Ramakrishnan, Sundararajan (2010-08). Case Studies on Clock Gating and Local Routign for VLSI Clock Mesh. Master's Thesis.

# etdChairOf[].label
Ni, Ruixiao (2014-05). On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs. Master's Thesis.

# etdChairOf[].label
Chen, Pu (2016-12). Security Attack Models for Split Manufacturing of Integrated Circuits. Master's Thesis.

# etdChairOf[].label
Wang, Jiafan (2017-08). Adaptive Integrated Circuit Design for Variation Resilience and Security. Doctoral Dissertation.

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Yang, Gongming (2014-05). NoC Resource Allocation Based on Physical Design Techniques. Master's Thesis.

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Yang, Yu (2011-05). Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems. Master's Thesis.

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Li, Chaofan (2018-05). Synthesis Techniques for Power-Efficient Integrated Circuits. Doctoral Dissertation.

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Singh, Amrinder (2010-08). Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. Master's Thesis.

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He, Hao (2016-11). Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems. Doctoral Dissertation.

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Panda, Reena (2011-12). A Branch-Directed Data Cache Prefetching Technique for Inorder Processors. Master's Thesis.

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Bhosekar, Shilpa (2018-08). Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip. Master's Thesis.

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Shim, Kyu-Nam 1978- (2012-12). Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits. Doctoral Dissertation.

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Gangrade, Rohit (2016-04). GPU Based Acceleration of SystemC and Transaction Level Models for MPSOC Simulation. Master's Thesis.

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Jindal, Tanuj (2010-08). Detecting Tangled Logic Structures in VLSI Netlists. Master's Thesis.

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Irukula, Shivaram (2015-08). Reinforcement Learning Based Controller For Precision Irrigation. Master's Thesis.

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Belsare, Aditya Sanjay (2014-08). Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms. Master's Thesis.

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Sharma, Prabal (2013-08). A Branch Predictor Directed Data Cache Prefetcher for Out-of-order and Multicore Processors. Master's Thesis.

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Won, Jae Yeon (2015-08). Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs. Doctoral Dissertation.

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Rasheed, Farah (2013-12). Artificial Neural Network Circuit for Spectral Pattern Recognition. Master's Thesis.