# overview
My research interests include computer-aided design of Very Large Scale Integration (VLSI) CAD, including physical design, parasitic extraction, fault diagnosis, variational analysis and process synthesis.

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4606 Distributed Computing And Systems Software

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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4009 Electronics, Sensors And Digital Hardware

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Partial Element Equivalent Circuit (peec) Modeling

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4.1 Discovery And Preclinical Testing Of Markers And Technologies

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Xi'an Jiaotong University - (Xi'an, China)

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Xi'an Jiaotong University - (Xi'an, China)

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University of Illinois at Urbana Champaign - (Urbana, Illinois, United States)

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Static compaction of delay tests considering power supply noise

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Institute of Electrical and Electronics Engineers (IEEE)

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A preconditioned hierarchical algorithm for impedance extraction of interconnects in packages

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Institute of Electrical and Electronics Engineers (IEEE)

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Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

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Institution of Engineering and Technology (IET)

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A More Effective $C_{eff}$ for Slew Estimation

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Institute of Electrical and Electronics Engineers (IEEE)

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Fast capacitance extraction using inexact factorization

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Institute of Electrical and Electronics Engineers (IEEE)

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Area minimization for hierarchical floorplans

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The Rectilinear Steiner Arborescence Problem Is NP-Complete

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Society for Industrial & Applied Mathematics (SIAM)

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Buffering Interconnect for Multicore Processor Designs

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Institute of Electrical and Electronics Engineers (IEEE)

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Process variation dimension reduction based on SVD

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A fast hierarchical algorithm for 3-D capacitance extraction

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Macro Model of Advanced Devices for Parasitic Extraction

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Institute of Electrical and Electronics Engineers (IEEE)

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Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost

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Institute of Electrical and Electronics Engineers (IEEE)

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An O(nlogn) time algorithm for optimal buffer insertion

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Buffer insertion in large circuits with constructive solution search techniques

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Association for Computing Machinery (ACM)

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Probabilistic Congestion Prediction with Partial Blockages

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Institute of Electrical and Electronics Engineers (IEEE)

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O(mn) Time Algorithm for Optimal Buffer Insertion of Nets with m Sinks

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Institute of Electrical and Electronics Engineers (IEEE)

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Model order reduction of linear networks with massive ports via frequency-dependent port packing

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Institute of Electrical and Electronics Engineers (IEEE)

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A circuit level fault model for resistive shorts of MOS gate oxide

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Institute of Electrical and Electronics Engineers (IEEE)

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Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials

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Institute of Electrical and Electronics Engineers (IEEE)

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Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method

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Institute of Electrical and Electronics Engineers (IEEE)

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A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction

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Institute of Electrical and Electronics Engineers (IEEE)

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A fast algorithm for area minimization of slicing floorplans

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Institute of Electrical and Electronics Engineers (IEEE)

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Multi-Scenario Buffer Insertion in Multi-Core Processor Designs

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Association for Computing Machinery (ACM)

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SRAM Methodology for Yield and Power Efficiency: Per-Element Selectable Supplies and Memory Reconfiguration Schemes

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Association for Computing Machinery (ACM)

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At-speed test for path delay faults using practical techniques

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Institute of Electrical and Electronics Engineers (IEEE)

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An Optimal Test Pattern Selection Method to Improve the Defect Coverage

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Institute of Electrical and Electronics Engineers (IEEE)

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A fast algorithm for optimal buffer insertion

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Institute of Electrical and Electronics Engineers (IEEE)

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Diagnosis of Wiring Networks: An Optimal Randomized Algorithm for Finding Connected Components of Unknown Graphs

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Society for Industrial & Applied Mathematics (SIAM)

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Optimal interconnect diagnosis of wiring networks

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Institute of Electrical and Electronics Engineers (IEEE)

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An O(bn(2)) time algorithm for optimal buffer insertion with b buffer types

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Institute of Electrical and Electronics Engineers (IEEE)

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A new methodology for interconnect parasitics extraction considering photo-lithography effects

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Institute of Electrical and Electronics Engineers (IEEE)

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Lagrangian Relaxation for Gate Implementation Selection

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Association for Computing Machinery (ACM)

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Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics

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Association for Computing Machinery (ACM)

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Institute of Electrical and Electronics Engineers (IEEE)

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An Efficient, Scalable Hardware Engine for Boolean SATisfiability

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Institute of Electrical and Electronics Engineers (IEEE)

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Minimizing defective part level using a linear programming-based optimal test selection method

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Institute of Electrical and Electronics Engineers (IEEE)

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Structural Diagnosis of Wiring Networks: Finding Connected Components of Unknown Subgraphs

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Society for Industrial & Applied Mathematics (SIAM)

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An efficient alorintham for RLC buffer insertion

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Institute of Electrical and Electronics Engineers (IEEE)

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The Impact of BEOL Lithography Effects on the SRAM Cell Performance and Yield

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Institute of Electrical and Electronics Engineers (IEEE)

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CodSim - A combined delay fault simulator

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A circuit level fault model for resistive opens and bridges

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Institute of Electrical and Electronics Engineers (IEEE)

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Longest path selection for delay test under process variation

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Institute of Electrical and Electronics Engineers (IEEE)

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On the complexity of switch programming in fault-tolerant configurable chips

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Institute of Electrical and Electronics Engineers (IEEE)

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Inductance extraction for interconnects in the presence of nonlinear magnetic materials

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A Vector-Based Approach for Power Supply Noise Analysis in Test Compaction

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Institute of Electrical and Electronics Engineers (IEEE)

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PARADE: PARAmetric delay evaluation under process variation

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On Crossing Sets, Disjoint Sets, and Pagenumber

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Optimal algorithm for area minimization of slicing floorplans

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Sparse transformations and preconditioners for 3-D capacitance extraction

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Institute of Electrical and Electronics Engineers (IEEE)

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Fast algorithms for slew-constrained minimum cost buffering

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Institute of Electrical and Electronics Engineers (IEEE)

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Ultra-fast interconnect driven cell cloning for minimizing critical path delay

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Association for Computing Machinery (ACM)

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Institute of Electrical and Electronics Engineers (IEEE)

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An Efficient Inductance Extraction Algorithm for 3-D Interconnects with Frequency Dependent Nonlinear Magnetic Materials

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Institute of Electrical and Electronics Engineers (IEEE)

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Optimal algorithms for finding connected components of an unknown graph

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A Fast Hierarchical Algorithm for Three-Dimensional Capacitance Extraction

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Institute of Electrical and Electronics Engineers (IEEE)

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Fast 3-D capacitance extraction by inexact factorization and reduction

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Institute of Electrical and Electronics Engineers (IEEE)

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A statistical fault coverage metric for realistic path delay faults

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Fast Characterization of Parameterized Cell Library

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Institute of Electrical and Electronics Engineers (IEEE)

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Fast inductance extraction of large VLSI circuits

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Institute of Electrical and Electronics Engineers (IEEE)

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Area minimization for hierarchical floorplans

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Circuit-wise buffer insertion and gate sizing algorithm with scalability

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Harvest rate of reconfigurable pipelines

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Institute of Electrical and Electronics Engineers (IEEE)

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Improving Boundary Element Methods for Parasitic Extraction** This research was supported by NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001.

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Institute of Electrical and Electronics Engineers (IEEE)

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K longest paths per gate (KLPG) test generation for scan-based sequential circuits

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Institute of Electrical and Electronics Engineers (IEEE)

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A circuit level fault model for resistive bridges

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Association for Computing Machinery (ACM)

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Longest-path selection for delay test under process variation

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Institute of Electrical and Electronics Engineers (IEEE)

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Making fast buffer insertion even faster via approximation techniques

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Impact of photolithography and mask variability on interconnect parasitics

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SPIE, the international society for optics and photonics

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A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

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Fast algorithms for slew constrained minimum cost buffering

# publications[].publisher
Association for Computing Machinery (ACM)

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A solenoidal basis method for efficient inductance extraction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

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An O(bn(2)) time algorithm for optimal buffer insertion with b buffer types

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks

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Efficient deterministic algorithms for embedding graphs on books

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Development of Fast 3D Parasitic Extraction using Hierarchical Method for Integrated Circuits and Packages

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

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Fast capacitance extraction in multilayer, Conformal and embedded dielectric using hybrid boundary element method

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SPIE, the international society for optics and photonics

# streetAddress
Texas A&M University; Electrical & Computer Engineering; 3128 TAMU

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Yan, Shu (2006-04). Efficient numerical methods for capacitance extraction based on boundary element method. Doctoral Dissertation.

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Chakraborty, Avijit (2015-11). Observability Driven Path Generation for Delay Test. Master's Thesis.

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Li, Zhixing (2014-12). Machine Learning Applied in 2D Parasitic Extraction. Master's Thesis.

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Yi, Yang (2011-02). Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. Doctoral Dissertation.

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Lu, Xiang (2006-04). Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits. Doctoral Dissertation.

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Zhou, Ying (2010-07). Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits. Doctoral Dissertation.

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Zhuang, Wei (2007-09). A 3-d capacitance extraction algorithm based on kernel independent hierarchical method and geometric moments. Master's Thesis.

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Bekal, Prasanna (2012-07). Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. Master's Thesis.

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Li, Zhuo (2006-04). Fast interconnect optimization. Doctoral Dissertation.

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Gupta, Kaustubh (2013-07). Design, Simulation and Modeling of Insulated Gate Bipolar Transistor. Master's Thesis.

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Yu, Fangqing (2004-09). A divide-and-conquer method for 3D capacitance extraction. Master's Thesis.

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Doddannagari, Uday (2009-05). A p-cell approach to integer gate sizing. Master's Thesis.

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Waghmode, Mandar (2007-04). Buffer insertion in large circuits using look-ahead and back-off techniques. Master's Thesis.

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Koteeswaran, Prabhavathi (2005-02). Fast dynamic force computation for electrostatic and electromagnetic conductors. Master's Thesis.

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Huang, Yi-Le (2012-02). An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization. Master's Thesis.