# overview
I'm interested in anything related to making computation go faster. My focus is on microarchitecture and the interaction between the compiler and the microarchitecture. I've been doing a lot of work in branch prediction and more recently caches. I'm known for inventing the perceptron branch predictor as well as for other research.

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4606 Distributed Computing And Systems Software

# keywords[]
4606 Distributed Computing And Systems Software

# keywords[]
4009 Electronics, Sensors And Digital Hardware

# keywords[]
4606 Distributed Computing And Systems Software

# educationAndTraining[].organization.label
The University of Texas at San Antonio - (San Antonio, Texas, United States)

# educationAndTraining[].organization.label
The University of Texas at Austin - (Austin, Texas, United States)

# educationAndTraining[].organization.label
The University of Texas at San Antonio - (San Antonio, Texas, United States)

# awardsAndHonors[].label
Faculty Early Career Development (CAREER) Program

# awardsAndHonors[].label
Faculty Early Career Development (CAREER) Program

# awardsAndHonors[].label
Faculty Early Career Development (CAREER) Program

# publications[].label
Locating anatomical landmarks for prosthetics design using ensemble neural networks

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Exploiting Procedure Level Locality to Reduce Instruction Cache Misses

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Characterizing the impact of last-level cache replacement policies on big-data workloads

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Composite Confidence Estimators for Enhanced Speculation Control

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Studying microarchitectural structures with object code reordering

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
CHIRP: Control-Flow History Reuse Prediction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Bara: Branch Agnostic Region Searching Algorithm

# publications[].label
Combining hyperblocks and exit prediction to increase front-end bandwidth and performance

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors* *A subset of the ideas presented in this paper appeared in an earlier workshop with unpublished proceedings

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
IMPROVING MEMORY RELIABILITY, POWER AND PERFORMANCE USING MIXED-CELL DESIGNS.

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
An Optimized Scaled Neural Branch Predictor

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
An evaluation infrastructure for power and energy optimisations

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Reducing the power and complexity of path-based neural branch prediction

# publications[].label
Exploiting Page Table Locality for Agile TLB Prefetching

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Idealized piecewise linear branch prediction

# publications[].label
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Morrigan: A Composite Instruction TLB Prefetcher

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A Two-Level Load/Store Queue Based on Execution Locality

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improving Multi-Core Performance Using Mixed-Cell Cache Architecture

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Sensible Energy Accounting with Abstract Metering for Multicore Systems

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Enhancing Signature Path Prefetching with Perceptron Prefetch Filtering

# publications[].label
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Neural methods for dynamic branch prediction

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
OH-SNAP: Optimized Hybrid Scaled Neural Analog Predictor

# publications[].label
Top Picks From the 2020 Computer Architecture Conferences

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Boolean Formula-based Branch Prediction for Future Technologies

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Insertion Policy Selection Using Decision Tree Analysis

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Improving cache performance by exploiting read-write disparity

# publications[].label
Code placement for improving dynamic branch prediction accuracy

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors

# publications[].label
A Method for Locating BK Anatomical Landmarks for a Laser Scanning Imager

# publications[].label
The impact of delay on the design of branch predictors

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improving Writeback Efficiency with Decoupled Last-Write Prediction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Bit-level Perceptron Prediction for Indirect Branches

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Insertion and promotion for tree-based PseudoLRU last-level caches

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Minimal Disturbance Placement and Promotion

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Program Phase Classification for Power Behavior Characterization

# publications[].label
Code placement for improving dynamic branch prediction accuracy

# publications[].label
Infrequent basic block-based program phase classification and power behavior characterization

# publications[].label
Rank idle time prediction driven last-level cache writeback

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Multiperspective Perceptron Predictor with TAGE

# publications[].label
Improving Cache Performance Using Read-Write Partitioning

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Toward an Evaluation Infrastructure for Power and Energy Optimizations

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
The Championship Simulator: Architectural Simulation for Education and Competition

# publications[].label
Low-Power. High-Performance Analog Neural Branch Prediction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
The impact of delay on the design of branch predictors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Building a low latency, highly associative dram cache with the buffered way predictor

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
The Impact of Cache Inclusion Policies on Cache Management Techniques

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Perceptron Learning for Reuse Prediction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
State-of-the-art graphic processing units (GPUs) can offer very high computational throughput for highly parallel applications using hundreds of integrated cores. In general, the peak throughput of a GPU is proportional to the product of the number of cores and their frequency. However, the product is often limited by a power constraint. Although the throughput can be increased with more cores for... chapter

# publications[].label
A Flexible Heterogeneous Multi-Core Architecture

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Workshop on Advancing Computer Architecture Research (ACAR-II) Laying a New Foundation for IT_ Computer Architecture for 2025 and Beyond

# publications[].label
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy

# publications[].label
Using dead blocks as a virtual victim cache

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Dynamic Branch Prediction with Perceptrons

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Improving writeback efficiency with decoupled last-write prediction

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Mixed-Signal Approximate Computation: A Neural Predictor Case Study

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Dynamically weighted ensemble neural networks for classification

# publications[].label
Evolution of the Samsung Exynos CPU Microarchitecture Industrial Product

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Thermometer: Profile-Guided BTB Replacement for Data Center Applications

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Reducing Network-on-Chip energy consumption through spatial locality speculation

# publications[].label
WADE: Writeback-Aware Dynamic Cache Management for NVM-Based Main Memory System

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Perceptron Learning for Predicting the Behavior of Conditional Branches

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Dead block replacement and bypass with a sampling predictor

# publications[].label
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Sampling Dead Block Prediction for Last-Level Caches

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Fast Path-Based Neural Branch Prediction

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Decoupled Cache Segmentation: Mutable Policy with Automated Bypass

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
A flexible heterogeneous multi-core architecture

# publications[].label
Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache

# publications[].publisher
Institute of Electrical and Electronics Engineers (IEEE)

# publications[].label
Revisiting memory management on virtualized environments

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Improved latency and accuracy for neural branch prediction

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
A Two-Level Load/Store Queue Based on Execution Locality

# publications[].publisher
Association for Computing Machinery (ACM)

# publications[].label
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor

# researcherOn[].label
EAGER: Deep Learning for Microarchitectural Prediction

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# researcherOn[].label
EAGER: Detecting and Avoiding Side-Channel Attacks with Security Conscious Prediction

# researcherOn[].awardedBy.label
National Science Foundation - (Arlington, Virginia, United States)

# streetAddress
Texas A&M University; Computer Science & Engineering; 3112 TAMU

# inTheNews[].label
Jiménez to help determine top computer architecture papers for publication

# inTheNews[].label
Jiménez inducted into International Symposium on Computer Architecture Hall of Fame

# inTheNews[].label
Jiménez receives High-Performance Computer Architecture Test of Time Award

# inTheNews[].label
Jiménez elevated to Institute of Electrical and Electronics Engineers Fellow

# inTheNews[].label
Jiménez honored as 2017 MICRO Hall of Fame inductee

# inTheNews[].label
Jiménez serves as program chair of HPCA 2017

# inTheNews[].label
Jiménez appointed interim chair of the Institute of Electrical and Electronics Engineers Computer Society Technical Committee on Computer Architecture

# inTheNews[].label
Daniel A. Jiménez Selected to Receive the IEEE Computer Society 2021 B. Ramakrishna Rau Award

# etdChairOf[].label
Jindal, Sangam (2018-08). Exploring Alternate Cache Indexing Techniques. Master's Thesis.

# etdChairOf[].label
Jindal, Sangam (2018-07). Exploring Alternate Cache Indexing Techniques. Master's Thesis.

# etdChairOf[].label
Teran, Elvira (2017-08). Principled Approaches to Last-Level Cache Management. Doctoral Dissertation.

# etdChairOf[].label
Tian, Yingying (2015-05). Reducing Waste in Memory Hierarchies. Doctoral Dissertation.

# etdChairOf[].label
Wang, Zhe (2014-08). Improving Processor Design by Exploiting Performance Variance. Doctoral Dissertation.

# etdChairOf[].label
Backes Drault, Luna B (2017-08). Evaluation of Cache Inclusion Policies in Cache Management. Master's Thesis.